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A low cost Async-Input for the SPI of 68HC812

Roland.Froehlich@t-online.de

The 68HC812 is a wonderful chip for many MIDI applications, but sometimes the 2 SCI ports
of the 68HC812 are not sufficient. For a new MIDI project I needed a third async input.
Commercial available SPI-Uarts are too expensive, so I found a low
cost alternative with a GAL16V8. This chip is clocked with 4 times the desired Baud rate,
it detects the start bit and supplies the SPI-Port with the Slave Select SS and the data sample
clock SCK. The SPI ports is configured as Slave, output of SPI is not used here.
Absolute Baud rate timing accuracy must be within 2.5% for safe operation, not a severe restriction.

                                Timing Diagram for SPIGAL
                                =========================

SCK is a square wave with frequency = Baud rate of async data line (Output from GAL).
The GAL-Clock is 4 * SCK, delivered from HC12-Timer output T7 (square wave, output compare with toggle and reset to 0 ).

            
DIN :
  ________    ________    ________    ________    ________    ________    ________    _____________________               ________  
 /        \  /        \  /        \  /        \  /        \  /        \  /        \  /        \            |             /        \ 
/          \/          \/          \/          \/          \/          \/          \/          \           |            /          \
\   D0     /\   D1     /\   D2     /\   D3     /\   D4     /\   D5     /\   D6     /\   D7     /    STOP   |    START   \   D0     /
 \________/  \________/  \________/  \________/  \________/  \________/  \________/  \________/            |_____________\________/ 
                                                                                                                                    
SCK:
      _____       _____       _____       _____       _____       _____       _____       _____                               _____      
     |     |     |     |     |     |     |     |     |     |     |     |     |     |     |     |                             |     |     
_____|     |_____|     |_____|     |_____|     |_____|     |_____|     |_____|     |_____|     |_____________________________|     |_ 
States:
60 1  2  3  4  5  6  7  8  9  10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31  0 32 32 32 36 48 52 56 60  1  2  3
                                         
SS:
__                                                                                                 ________________________
  |                                                                                               |                        |
  |_______________________________________________________________________________________________|                        |__________
   

                                Description of operation
                                ========================
The GAL performs a 6 Bit State-Machine with state-vector (A5=SS,A4,A3,A2,A1=SCK,A0).
In state=32 (idle) the start bit (DIN=0) is evaluated, and if not present, this state is repeated.
If present, then the next checkpoint is state=48 for validation of the start bit (this is the
nominal data sample point). If not more present, then goto idle state=32, else advance in
the sample process. In state=1 is the Slave Select SS activated, and in state=2 the first
sample-clock SCK for the SPI is generated (SPI samples at positive edge of SCK). There are 8 SCK
edges for 8 data bits (LSB first shifted in). After this all, the SS is inactivated. At this point the data byte is
available in the SPI data register for read in polling or interrupt mode.
All others as listed above (illegal states) are jumping to the idle state=32 (i.e. hunt mode).
A validation of the Stop bit is not made because error handling is not fruitfull in this small application
and violations are not typical here. 
The minimalistic design shows no extravagancy because the possible 8 product terms are reached,
but it works, fine. The secret is the coding and sequencing of states, sharing state variables with
output bits, to fit in the given chip architecture. This task can be very time consuming or leads to
a bigger chip if you don't see the possibilities while thinking about the project.

The SPI configuration must be ( SP0CR1 ):
spe = 1 ; SPI enabled
mstr = 0 ; Slave mode
cpol = 0 ; clock polarity
cpha = 0 ; clock phase
lsbf = 1 ; transfer LSB first - as usual for async protocol

The incoming async data line must be synchronized by the GAL because if setup times to GAL-clock
are violated, proper operation of the state machine is not guaranteed. There are different product terms
builded with the DIN signal which have to stay in consistency each to other. 
The synch is made with a transparent D-Latch inside the GAL, the Latch-Enable is the GAL-clock (Pin1 --> Pin2).
If clock is low the data is freezed internally (DIN pin) and fullfills the setup time for the next rising clock edge.
However the SPI data input MOSI sees the original data.
This design MUST be made with the option "retain redundancy" or "MINIMIZE_OFF" , otherwise the D-Latch is glitchy and
the whole circuit can be misoperating. DIN must be synthesized with 3 product terms! Check it !!!

The ABEL design file for this chip is spigal.abl and the resulting Jedec is spigal.jed
free at your pleasure.

                                Circuit and connection diagram
                                ==============================
                                                              ^ +5V		                                            
                                                              |                                         c                   
                                ------------------            |			                        l  C                                                      
 Port T7     >-------x---- CLK--|> 1          20 |-Vcc--------x                                      M  o  L     !                                                    
                     |          |                |            |                                      I  c  O     D                                                
                      ---- CLK1-|  2          19 | DIN       ---                                     D  k  C     I                                                  
                                |                |           --- 0.1uF                               I  1  K     N                                                
 RS-Data-In  >-------x---- MIDI-|  3          18 | (NC)       |                                    /----------------                                              
 (TTL)               |          |                |           ---                                  /  3  2  1 20 19 |                                              
                     |     (NC) |  4          17 | !A0                                            |                |                                                
                     v          |                |                                                |  4          18 |                                              
                  SPI/MOSI (NC) |  5    16V8  16 | !A2                                            |                |                                                          
                                |                |                                                |  5          17 | !A0                                          
                           (NC) |  6          15 | !A3                                            |                |                                                
                                |                |                                                |  6          16 | !A2                                          
                           (NC) |  7          14 | !A4                                            |                |                                                
                                |                |                                                |  7          15 | !A3                                          
                           (NC) |  8          13 |-!SS -----------> SPI/ SS                       |                |                                               
                                |                |                                                |  8          14 | !A4                                          
                           (NC) |  9          12 |-!SCK ----------> SPI/ SCK                      |                |                                              
                                |                |                                                |  9 10 11 12 13 |                                              
                        --- GND-|  10         11 |-!OE--                                          ------------------                                                          
                        |       |                |     |                                                      !  !                                                
                        |       ------------------     |                                                      S  S                                                
                       ---                            ---                                                     C  S                                                
                                                                                                              K

Any questions or suggestions ?
Email me: Roland.Froehlich@t-online.de