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10Hz - 100KHz D.D.S. Function Generator

Picture 1

Design and Development

George Vastianos
Electronics Engineer BSc.
Dipl. from Electronics Department,
Faculty of Technological Applications,
Technological Educational Institute of Piraeus, Greece

www.vastianos.com

Table of contents

0. Introduction
1. Technical specifications
2. Sinusoidal waveform direct digital synthesis
3. The hardware of the project
4. The software of the project
5. References
Appendix A. AT90S1200 microcontroller datasheet
Appendix B. ML2037 sine wave generator datasheet

0. Introduction

The presented project is a function generator for sinusoidal and square signals production. The output frequency covers the range from 10 Hz to 100 KHz with a step of 2 Hz.

The waveform synthesis is based on the D.D.S. technique (Direct Digital Synthesis) and the output frequency is selected through a microcomputer with an embedded thumb wheel keyboard.

1. Technical specifications

  1. Output Frequency: 10 Hz - 100 KHz (step 2 Hz)
  2. Output Voltage:
    • Sinus: 0 - 20 Vp-p
    • Square: 0 - 20 Vp-p
    • TTL: 5 V
  3. Output Resistance: 1 KOhms

2. Sinusoidal waveform direct digital synthesis

A complete sinusoidal waveform can be synthesized through a D.D.S. system. This system uses a group of 2^21 phases (time slots) and a 16 bit data latch defines how many of them will be contained between two successive synchronization pulses. If the 16 bit data latch contains low numerical values then the output frequency will be low and if the 16 bit data latch contains high numerical values then the output frequency will be high.

PDF Figure 1. Detailed Block Diagram of the ML2037. (58,3 KBytes)

In figure 1 the 21 bit adder and the 21 bit latch make the phase accumulator of the D.D.S. system, which shows every time the current phase. The phase accumulator is synchronized with the Fref.

Fref = Fclk(in) / 2

The value that is stored in the 16 bit data latch is added with the value of the accumulator every four clock periods of Fclk(in). The output frequency is equal to the rate of the accumulator's overflow and can be calculated from the following formula:

Fout = (Fclk(in) * ([D15 - D0]dec)) / 2^22

The duration of each phase follows the (one unit) changing of the 21 bit latch and can be calculated from the following formula:

DF = Fclk(in) / 2^22

The minimum output frequency is:

Fout(min) = DF

The maximum output frequency is:

Fout(max) = Fclk(in) / 2^6

Only the eight MSBits of the total of 21 bits of the phase accumulator are used for the next stages of the synthesis. From these eight bits the 1st MSBit is used as a sign bit and the 2nd MSBit is used as a quadrant bit. The quadrant complementor (with the use of the quadrant bit) drives the ROM (which has a look-up table of 64 steps [Pi/2]) and produces the 128 steps of the period [Pi]. After that, the sign bit and the sign complementor produce the total 256 steps of the period [2*Pi]. The output of the sign complementor drives the analog to digital converter (through the output latch) and the produced analog signal enters a low pass filter. Finally, the filtered signal is the synthesized sinewave.

3. The hardware of the project

Picture 2
(Pic 2. The hardware of the D.D.S. Function Generator)

PDF Figure 2. D.D.S. Function Generator : Block Diagram. (25,8 KBytes)

The block diagram (figure 2) shows the four units of the circuit :

  1. Microcomputer unit : This unit is used for the output frequency selection and produces the driving signals for the D.D.S. unit.
  2. D.D.S. unit : This unit is used for the sinewave synthesis. The frequency of this sinewave is defined by the microcomputer.
  3. Sine, Square, TTL unit : This unit adapts the sinusoidal waveform, that is produced from the D.D.S. unit, to the supported functions.
  4. Power supply unit : This unit produces +15V, -15V, +5V for the supply of the above units.

PDF Figure 3. D.D.S. Function Generator : Microcomputer Unit. (47,6 KBytes)

The schematic circuit of the microcomputer unit is shown in figure 3. This unit is based on the microcontroller IC1 which is a member of Atmel's AVR RISC family. The microcontroller used, is the AT90S1200 and its task is to read the selected frequency and drive the D.D.S. unit.

The output frequency is selected, by the user, through a group of 6 thumb wheel switches (TW1-TW6). The outputs of these switches are connected through the diodes D1-D24 to the 4 MSBits of portB (PB4-PB7). The common pin of each thumb wheel (COM) is connected to an output of portD. The group of the 6 thumb wheels use the pins PD0-PD5.

The algorithm of the thumb wheel keyboard reading is easy. First the microcontroller sets only one of the outputs PD0-PD5 and resets the rest. With this tip, the microcontroller reads from PB4-PB7 the value of the activated thumb wheel. After the activation of the 6 thumb wheels we have the 6 digit BCD numerical value of the selected frequency.

The output PD6 drives a LED to inform the user if the selected frequency exceeds the supported range. And the outputs PB0-PB2 drive the D.D.S. unit through the ISO1-ISO3 optocouplers.

The capacitor C1 is used as a decoupling capacitor to improve the stability of the circuit and the resistor R1 is used to set the microcontroller in RUN mode. The quartz Y1 with the capacitors C2 and C3 make the microcomputer's oscillator circuit. The microcontroller can be programmed through the ISP connector (6 pin header).

PDF Figure 4. D.D.S. Function Generator : Direct Digital Synthesizer Unit. (31,6 KBytes)

The schematic circuit of the D.D.S. unit is shown in figure 4. This unit is based on the ML2037 of Micro Linear (IC2) which is a "500 KHz, Serial Input, Programmable Sine Wave Generator". The capacitors C4 and C5 are used as decoupling capacitors to improve the stability of the circuit.

The quartz Y2 allows the generator to cover the range of 10 Hz to 100 KHz with a step of 2 Hz and the resistors R6, R7, R8 are used as pull-down resistors to terminate the inputs SENABLE, SCLK, SDATA of IC2.

The output waveform of D.D.S. unit is sinusoidal with an amplitude of 2 Vp-p and has a d.c. offset of 1.5 V.

PDF Figure 5. D.D.S. Function Generator : Sine-Square-TTL Unit. (49,9 KBytes)

The schematic circuit of the sinus, square, TTL unit is shown in figure 5. This unit is separated in three subunits.

The sinus subunit uses two opamps IC3 and IC4 (TL081) and transforms the waveform to a sinusoidal waveform with adjustable amplitude 0 - 20 Vp-p and no d.c. offset.

The capacitor C6 is used to cut the d.c. offset and the resistor R9 works as an input resistance of IC3. The R10 and R11 set the amplitude gain of Av = 10. The trimmer TR1 and the potentiometer P1 adjust the output voltage to be between 0 and 20 Vp-p. The R12 with the resistance between the pins 2 and 3 of P1, work as input resistance of IC4. The IC4 is connected as a buffer.

The square subunit uses two opamps IC5 and IC6 (AD829) and transforms the waveform to a square waveform with adjustable amplitude 0 - 20 Vp-p and no d.c. offset.

The capacitor C11 is used to cut the d.c. offset and the resistor R14 works as an input resistance of IC5. The IC5 is connected as comparator and adapts the sinewave to squarewave with 27 Vp-p amplitude. The trimmer TR2 and the potentiometer P2 adjust the output voltage to be between 0 and 20 Vp-p. The R15 with the resistance between the pins 2 and 3 of P2, work as an input resistance of IC6. The IC6 is connected as a buffer through the R17.

The TTL subunit uses the digital shmitt trigger 74HC14 (IC7) and transforms the waveform to a square waveform which is TTL compatible.

The trimmer TR3 and the resistor R18 are used to adjust the Duty Cycle at 50%. The IC7 contains 6 inverters - shmitt triggers (IC7A-IC7F) and for this reason the input waveform passes through two shmitt triggers to cancel the inverting.

The capacitors C7, C8, C9, C10, C12, C13, C14, C15, C16 are used as decoupling capacitors to improve the stability of the circuit and the resistors R13, R16 work as output resistance of the function generator (1 KOhms). The function is selected through the switches SW1, SW2.

PDF Figure 6. D.D.S. Function Generator : Power Regulated Supply Unit. (51,1 KBytes)

The schematic circuit of the power supply unit is shown in figure 6. The supply voltage is provided from a 2x18 Vac transformer, rectified by the bridge of D25-D28 and filtered by C19, C22. Finally we have the production of +25.4 Vdc and -25.4 Vdc.

The voltages that we need to supply all the above units are : +15 Vdc and -15 Vdc (for the opamps) and +5 Vdc (for the digital parts).

The voltage of +25.5 V drives the regulator IC8 (LM7815) and is stabilized at +15 V. The voltage of -25.5 V drives the regulator IC10 (LM7915) and is stabilized at -15 V. And the voltage of +15 V drives the regulator IC9 (LM7805) and is stabilized at +5 V.

The capacitors C23, C27, C31 and C24, C25, C28, C29, C32, C33 are used as decoupling capacitors to improve the stability of the regulators. The trimmers TR4, TR5, TR6 are used for the final adjusting of the stabilized voltages. And the capacitors C26, C30, C34 are used to cut off the thermal noise that is produced from the trimmers TR4-TR6.

Picture 3
(Pic 3. A closer view of the PCB)

ZIP PCB Schematics & Drawing Files In ORCAD7 Format. (67,6 KBytes)

4. The software of the project

The microcontroller' s software has been developed in Assembly (of Atmel's AVR Family) and its source code can be found in Listing 1.

Listing 1:

; *******************************************
; * 10Hz - 100KHz D.D.S. FUNCTION GENERATOR *
; *       Microcontroller Source Code       *
; *              Version : 1.0              *
; *          1998 George Vastianos         *
; *******************************************

; Note : 
; This version does not support the frequency 
; limits checking, so the LED is always on.

.include "1200def.inc"

	rjmp	RESET	;reset handle

;*****************************************************
;* "BCD2BIN" - BCD to 16-Bit Binary Conversion       *
;*                                                   *
;* This subroutine converts a 6-digit packed BCD     *
;* number represented by 3 bytes (fBCD2:fBCD1:fBCD0) *
;* to a 16-bit number divided by 2 (tbinH:tbinL).    *
;*****************************************************
.def	fBCD0	=r16		;BCD value digits 1 and 0
.def	fBCD1	=r17		;BCD value digits 3 and 2
.def	fBCD2	=r18		;BCD value digits 5 and 4
.def	tbinL	=r19		;Low  byte of binary result (same as mp10L)
.def	tbinH	=r20		;High byte of binary result (same as mp10M)
.def	mp10L	=r19		:Low  byte of number to be multiplied by 10
.def	mp10M	=r20		:Mid  byte of number to be multiplied by 10
.def	mp10H	=r21		;High byte of number to be multiplied by 10
.def	copyL	=r22		;temporary register
.def	copyM	=r23		;temporary register
.def	copyH	=r24		;temporary register
.def	adder	=r25		;value to add after multiplication	
mul10a:	
	swap	adder
mul10b:	
	mov	copyL,mp10L	;make copy
	mov	copyM,mp10M
	mov	copyH,mp10H
	lsl	mp10L		;multiply original by 2
	rol	mp10M
	rol	mp10H
	lsl	copyL		;multiply copy by 2
	rol	copyM
	rol	copyH		
	lsl	copyL		;multiply copy by 2 (4)
	rol	copyM
	rol	copyH		
	lsl	copyL		;multiply copy by 2 (8)
	rol	copyM
	rol	copyH		
	add	mp10L,copyL	;add copy to original
	adc	mp10M,copyM
	adc	mp10H,copyH	
	andi	adder,0x0f	;mask away upper nibble of adder
	add	mp10L,adder	;add lower nibble of adder
	clr	adder	
	adc	mp10M,adder		
	adc	mp10H,adder		
	ret	
BCD2BIN:
	clr	mp10H		
	clr	mp10M		
	mov	adder,fBCD2
	swap	adder
	andi	adder,0x0f	;mask away upper nibble of adder	
	mov	mp10L,adder	;mp10H:mp10M:mp10L = a	
	mov	adder,fBCD2
	rcall	mul10b		;mp10H:mp10M:mp10L = 10a+b
	mov	adder,fBCD1
	rcall	mul10a		;mp10H:mp10M:mp10L = 10(10a+b)+c
	mov	adder,fBCD1
	rcall	mul10b		;mp10H:mp10M:mp10L = 10(10(10a+b)+c)+d
	mov	adder,fBCD0		
	rcall	mul10a		;mp10H:mp10M:mp10L = 10(10(10(10a+b)+c)+d)+e
	mov	adder,fBCD0
	rcall	mul10b		;mp10H:mp10M:mp10L = 10(10(10(10(10a+b)+c)+d)+e)+f
	clc
	ror	mp10H		;Divide result by 2
	ror	mp10M
	ror	mp10L
	ret

;*********************************************
;* "READTWS" - Read Thunpweel Switches       *
;*                                           *
;* This subroutine converts a 6-digit packed *
;* BCD number represented by 3 bytes         *
;* (fBCD2:fBCD1:fBCD0) to a 16-bit number    *
;* divided by 2 (tbinH:tbinL)                *
;*********************************************
.def	fBCD0	=r16		;BCD value digits 1 and 0
.def	fBCD1	=r17		;BCD value digits 3 and 2
.def	fBCD2	=r18		;BCD value digits 5 and 4
.def	thsl	=r19
.def	thrd	=r20	
READTWS:
	clr	fBCD0		;Clear fBCD0
	clr	fBCD1		;Clear fBCD1
	clr	fBCD2		;Clear fBCD2
	in	thsl,PIND	;Read TW1 & TW2
	andi	thsl,0x40
	ori	thsl,0x01
	out	PORTD,thsl
	rcall	delay
	in	thrd,PINB
	andi	thrd,0xf0
	swap	thrd
	or	fBCD0,thrd
	rcall	delay
	in	thsl,PIND
	andi	thsl,0x40
	ori	thsl,0x02
	out	PORTD,thsl
	rcall	delay
	in	thrd,PINB
	andi	thrd,0xf0
	or	fBCD0,thrd
	rcall	delay
	in	thsl,PIND	;Read TW3 & TW4
	andi	thsl,0x40
	ori	thsl,0x04
	out	PORTD,thsl
	rcall	delay
	in	thrd,PINB
	andi	thrd,0xf0
	swap	thrd
	or	fBCD1,thrd
	rcall	delay
	in	thsl,PIND
	andi	thsl,0x40
	ori	thsl,0x08
	out	PORTD,thsl
	rcall	delay
	in	thrd,PINB
	andi	thrd,0xf0
	or	fBCD1,thrd
	rcall	delay
	in	thsl,PIND	;Read TW5 & TW6
	andi	thsl,0x40
	ori	thsl,0x10
	out	PORTD,thsl
	rcall	delay
	in	thrd,PINB
	andi	thrd,0xf0
	swap	thrd
	or	fBCD2,thrd
	rcall	delay
	in	thsl,PIND
	andi	thsl,0x40
	ori	thsl,0x20
	out	PORTD,thsl
	rcall	delay
	in	thrd,PINB
	andi	thrd,0xf0
	or	fBCD2,thrd
	rcall	delay
	ret

;*********************************
;* "delay" - Small Delay Routine *
;*********************************
.def	temp	=r26
.def	temp2	=r27
delay:
	ldi	temp,$ff
	ldi	temp2,$00
lp1:	dec	temp
	cpse	temp,temp2
	rjmp	lp1	
lp2:	ret

;******************************************
;* "SEND2DDS" - Send Data To DDS          *
;*                                        *
;* This subroutine sends the contents of  *
;* the tbinH:tbinL (DDSH:DDSL) to the DDS *
;******************************************
.def	DDSL	=r21
.def	DDSH	=r22
.def	count	=r23
SEND2DDS:
	in	temp,PINB
	andi	temp,0x00
	ori	temp,0x04
	out	PORTB,temp
	rcall	delay
	rcall	delay
	rcall	delay
	ldi	count,0x10
lp3:	in	temp,PINB
	andi	temp,0x04
	ori	temp,0x02
	out	PORTB,temp
	rcall	delay
	rcall	delay
	rcall	delay
	ror	DDSH
	ror	DDSL
	brcs	lp4
	rjmp	lp5
lp4:	in	temp,PINB
	andi	temp,0x06
	ori	temp,0x01
	out	PORTB,temp
	rcall	delay
	rcall	delay
	rcall	delay
	rjmp	lp6
lp5:	in	temp,PINB
	andi	temp,0x06
	out	PORTB,temp
	rcall	delay
	rcall	delay
	rcall	delay
	rjmp	lp6
lp6:	in	temp,PINB
	andi	temp,0x05
	out	PORTB,temp
	rcall	delay
	rcall	delay
	rcall	delay
	dec	count
	ldi	temp,0x00	
	cpse	count,temp
	rjmp	lp3
	rjmp	lp7	
lp7:	in	temp,PINB
	andi	temp,0x00
	out	PORTB,temp
	rcall	delay
	rcall	delay
	rcall	delay
	ret

;****************
;* Main Program *
;****************
RESET:
	ldi	temp,0x0f
	out	DDRB,temp
	ldi	temp,0x00
	out	PORTB,temp
	ldi	temp,0xff
	out	DDRD,temp
	ldi	temp,0x00
	out	PORTD,temp
loop:	rcall	READTWS
	rcall	BCD2BIN
	mov	DDSH,tbinH
	mov	DDSL,tbinL
	rcall	SEND2DDS
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rcall	delay
	rjmp	loop
;******************
;* End Of Program *
;******************

ASM Microcontroller Source Code File. (6,13 KBytes)

The microcontroller can be programmed with a simple AVR programmer or "on board" through the ISP connector.

5. References

George Vastianos, "10Hz - 100KHz D.D.S. Function Generator", Project Book, (Greek Edition), Athens-GR, December 1998, 193p.

Appendix A. AT90S1200 microcontroller datasheet

ATMEL, "Datasheet of AT90S1200: 8-bit AVR Microcontroller with 1K Byte of In-System Programmable Flash (Summary)", October 2000, 10p, Filename : ddsfgen_0838s.pdf (380 KBytes).

Appendix B. ML2037 sine wave generator datasheet

Fairchild Semiconductors, "Datasheet of ML2037: 500KHz, Serial Input, Programmable Sine Wave Generator With Digital Gain Control", October 1998, 10p, Filename : ddsfgen_ML2037.pdf (213 KBytes).