Multiplexing To Get More Outputs

by Tom Dickens

Introduction

Assuming that your system has some digital outputs, but you need more outputs for the current project you're working on, what do you do? This article will explain how to add as many digital outputs to your system as you desire. The types of systems I'm referring to are typically microcontrollers, such as the 68HC11, 68HC12, 68332, PIC chip, BASIC Stamp, ATMEL processor, and a host of others. This technique can also be applied to the parallel-port output of a PC. I will present this information in a generic manner, which should apply to any target system. The usage examples will be in pseudo-code and then in assembly code which are specific to the 68HC11, but this could be easily adapted to any other system.

The Concept

You can use a limited number of digital outputs, along with a simple digital circuit and a simple program, to control as many digital outputs as you desire. The type of circuit we're talking about here is a multiplexer, or MUX for short. With a MUX circuit, you take your digital outputs from your system and group them into two types, data lines and address lines. Depending on the number of system digital outputs you have to work with, and how you group them into address lines and data lines, you can get various numbers of resulting MUX outputs, plus varying complexity of the required digital circuit.

 

 

 

 

 

 

 

Figure 1. Concept of system outputs generating more outputs using a multiplexer circuit.

 

Let's walk through an example using 8 system digital output lines to see the possibilities:

 

Table 1. Address/Data combinations for 8-bit output.

The top row in Table 1 shows us that if we use all 8 lines as data lines, we get 8 resulting output lines (and our circuit is very simple, just wires). The next row uses one of the lines as an address and the other 7 as data. With the address set to 0, we can specify 7 data values and then with the address set to 1 we can specify 7 more data vales, giving us 14 resulting output lines. Continuing down the rows we see that the same 8 system outputs can generate up to 128 resulting outputs. Wow! There is a generic equation to determine the resulting number of outputs we would get. Given N as the total number of system outputs, A is the number of address lines, D is the number of data lines, where A + D = N, we can calculate:

            2^A * D = R (the resulting output lines)                                             Equation 1.

 

Choosing N=8 we can vary A, which generates D and R.

Figure 2. Plot of data from Table 1; Address to resulting outputs for 8-bit multiplexer.

We can clearly see in the plot in Figure 2 that the more lines we use as addresses, the more resulting outputs we will generate. We can, using Equation 1, see the number of outputs we can get for different numbers of address and data lines.

However, there is a price to be paid for this; the complexity of the required digital circuit, and the complexity and time required to execute the resulting driving program, goes up with the number of address lines. Another factor is the type and configuration of the digital chips that are available to use in the support circuit. In a minute we will look at practical limitations and implementations.

Considering using from 4 to 12 output lines. Figure 3 shows how many outputs could be generated. The maximum for 11 bits is 1024, and for 12 bits is 2048, which is a very large number of outputs from a small number of original output lines

 

Figure 3. Possible number of outputs for 4 through 12 lines.

Before we jump into building a 12-to-2028-output circuit, let's first consider the building blocks available and the hardware/software complexity required, so we can design a reasonable system which can be easily built and easily used, but also gives us a good expanded-output capability.

Circuit Building Blocks

The digital chips available that we will use to build up our multiplexing output circuit are the 74HCnnn family of chips, but similar functionality can be found in the other 74-series (74LS for example), and also in the old 4000-series CMOS devices.

Address Lines

For the address lines, we need to "fan out" the address into N control lines (we'll see why in a moment). The type of device we want here is called a "decoder," also referred to as a "demultiplexer." These take A address lines, and produce 2A outputs, where one output as specified by the address is at one logic level (typically Low), and all the other outputs are at the other logic level (typically High). The two most-used 74HCnnn devices for this are the 74HC138 (1-of-8 decoder) and the 74HC154 (1-of-16 decoder). The '138 (short for 74HC138) takes 3 address lines and produces 8 control lines, while the '154 takes 4 address lines and produces 16 control lines. The typical logic-symbol for such a device is shown in Figure 4.

Figure 4. Decoder logic symbol.

 

The 3 address lines are A0, A1, and A2. There are also 3 enable lines which can be used to configure multiple '138 devices to directly handle up to 6 input address. To enable a device, tie E1 and E2 low and E3 high. The 8 generated outputs are Y0 trough Y7. The circles on the diagram indicate that the active level for that pin is inverted, thus we can see that E1 and E2 should be low (inverted), E3 should be high, and the output addressed in Y0 to Y7 will be low (all other 7 outputs will be high).

Table 2 is a truth-table for the 74HC138, showing the states of the outputs for all input combinations. The '-' entries are "don't care" states. H is logic high, or 5 volts. L is logic low, or 0 volts. Note that any enable input can disable the device.

Table 2. Truth-table for the 74HC138 decoder/demultiplexer..

Data Lines

For the data lines, we need to capture the data and hold their values until we want it to change. The type of device we want here is called a "latch" or a "flip-flop" (FF). These devices take D data lines and will capture their values when commanded to do so. The commonly-used 74HCnnn devices for this are the 74HC74 (dual flip-flop, 2 in one chip), 74HC173 (quad flip-flop, 4 in one chip), 74HC174 (hex flip-flop, 6 in one chip), and the 74HC374 (octal flip-flop, 8 in one chip).

Figure 4. 8-bit latch logic symbol.

These devices have data inputs, data outputs, a clock input, and output enable inputs. The data on the inputs is captured and presented at the outputs when the cock input goes from a low to a high state. Tie the output enable(s) to enable the device (low on the '374).

Figure 4 shows the typical logic-symbol for a 74HC374 8-bit latch.

 

There is a device, the 74HC574 which is identical in functionality to the '374, but all the data inputs are on the left side of the chip, and all the outputs are on the right side of the chip. This makes it much easier to wire up; many people commonly use the '574 for this reason even though the two devices are logically identical.

Putting it All Together

How does this work? Let's use a example to walk through the setup and use of a typical system.

The Hardware

Assume we have 8 system outputs (O0 trough O7) from a microcontroller and we want more outputs. Let's call 2 of these outputs address lines, and 6 of them data lines. With 2 address lines, we will generate 4 control outputs (Y0 through Y3 in Figure 5). Each of these is connected to the clock input of one of the flip-flip devices. The 6 data lines (O2 through O7) are connected to the data input lines (D0 through D5) of all 4 of the hex flip-flops. The resulting outputs are generated from the 4 flip-flops as outputs R0 through R23. Thus, with 5 common off-the-shelf chips, we have turned 8 outputs into 24 outputs.

Figure 5. 8-bit to 24-bit multiplexer circuit.

The Software

To use the circuit detailed above, the software in the system must know about the specific hardware connected to the 8-bit output lines. Given a 24-bit number to output, what does the software need to do? Simply stated:

 

We need to present the correct data to the 6 data lines and then cause the correct output from the ‘138 to go from low to high to capture the data on the data lines into the correct latch.

 

OK, we’ll walk through this specific example step-by-step. But first, we need to diverge into the topic of Gray Codes.  Frank Gray, a research scientist at Bell Labs, on 3/17/1953, filed patent no. 2,632,058 for the Gray code encoding vacuum tube. We’re not using vacuum tubes, but the principle is very important here too. Gray code is a sequence of binary numbers such that any two consecutive numbers differ only in a single position. Let’s consider the repeating cycle of numbers 0 through 3 as seen in Table 3.

Table 3. Gray Code for a 2-bit number cycling from top to bottom.