A Color Vision System for Embedded Robotics Applications

From their web site, Xilinx provides several excellent application notes describing the different algorithms used to configure their FPGAs. The 'C' code to implement one such algorithm / interface is provided below:

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extern void feed_watchdog(void);
extern void delay_usec(unsigned short times);
extern void delay_msec(unsigned short times);

#define FPGA_PGM     0x0001  /*PP0*/
#define FPGA_INIT    0x0002  /*PP1*/
#define FPGA_CLK     0x0004  /*PP2*/
#define FPGA_DONE    0x0008  /*PP3*/
#define FPGA_DATA    0x0010  /*PP4*/

// the following line maps PADAT to a bank of general purpose IO pins
#define PADAT  cf_imm.pp.PADAT

int loadFpgaConfig(void)
{
    unsigned short data;
    unsigned short value;
    unsigned long i;
    int j;

    cf_imm.pp.PADDR = 0xF5F5;  //A 1 configures as output 
                              //bit 0 - PP0, FPGA_PGM, output
                              //bit 1 - PP1, FPGA_INIT, input
                              //bit 2 - PP2, FPGA_CLOCK, output
                              //bit 3 - PP3, FPGA_DONE, input
                              //bit 4 - PP4, FPGA_DATA, output
                              //bit 5 - PP5, NC
                              //bit 6 - PP6, NC
                              //bit 7 - PP7, Heartbeat LED, output
                              //bit 8 - PP0, FPGA2_PGM, output
                              //bit 9 - PP1, FPGA2_INIT, input
                              //bit 10- PP2, FPGA2_CLOCK, output
                              //bit 11- PP3, FPGA2_DONE, input
                              //bit 12- PP4, FPGA2_DATA, output
                              //bit 13- PP5, NC
                              //bit 14- PP6, NC
                              //bit 15- PP7, NC

    feed_watchdog();    
    
    PADAT = 0x0100;         //set /PGM low to start FPGA program sequence

    delay_usec(10);     //hold low for about 10 usecs
    
    value = FPGA_PGM;    //de-asserts /PGM to begin programming
    PADAT = value | 0x100;
    feed_watchdog();    
    #ifndef FPGA_SIMULATION
        system_usec_timer = 0;
        while ((PADAT & FPGA_INIT) == 0)
        {
            if (system_usec_timer > 500)
            {
                feed_watchdog();
                dprintf("FPGA Config Error: timed out waiting for memory clear\n\r");
                return(1);
            }
        }
    #endif
    
    for(i=0;i> 1;
        }
    }
    
    PADAT = FPGA_PGM | 0x100; //leave /PGM de-asserted    
    feed_watchdog();    
    //normally we'd wait for the DONE signal to go high before moving on...
    //also, if /INIT is low at this time, we have a programming error.
    #ifndef FPGA_SIMULATION
        system_usec_timer = 0;
        while ((PADAT & FPGA_DONE) == 0)
        {
            feed_watchdog();
            if ((PADAT & FPGA_INIT) == 0)
            {
                feed_watchdog();
                dprintf("FPGA Config Error: INIT indicates bad CRC\n\r");
                return (2);
            }
            if (system_usec_timer > 50000)
            {
                feed_watchdog();
                dprintf("FPGA Config Error: timed out waiting for DONE to go high\n\r");
                return (3);
            }
        }
    #endif

    feed_watchdog();
    return(0);
}

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