A Color Vision System for Embedded Robotics Applications

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Verilog FPGA I2C Instantiation:


parameter I2C_REG_ADDR1 = 12'h001;
parameter FPGA_RST_ADDR = 16'h0009;


reg [1:0] qual_counter;
wire qual_data;
wire [7:0] i2c1_data_out;
wire scl1_pad_o;
wire scl1_padoen_o;
wire sda1_pad_o;
wire sda1_padoen_o;
wire scl1_pad_i;
wire sda1_pad_i;
wire i2c1_irq_o;
wire ack_1;

always @(posedge sys_clock)
begin
	if(proc_cs)
		qual_counter[1:0] <= #1 2'b00;
	else
		qual_counter[1:0] <= qual_counter[1:0] + 2'b01;
end

assign #1 qual_data = ((qual_counter[1:0] == 2'b01) && (~proc_rw));

assign #1 vip1_scl = scl1_padoen_o ? 1'bz : scl1_pad_o;
assign #1 vip1_sda = sda1_padoen_o ? 1'bz : sda1_pad_o;
assign #1 scl1_pad_i = vip1_scl;
assign #1 sda1_pad_i = vip1_sda;
assign #1 proc_data[7:0] = (~proc_cs && proc_rw && (proc_addr[15:4] == I2C_REG_ADDR1)) ?
	i2c1_data_out[7:0] : 8'bzzzzzzzz;

i2c_master_top my_i2c1(
	.wb_clk_i(sys_clock),
	.wb_rst_i(1'b0),
	.arst_i((proc_addr[15:0] == FPGA_RST_ADDR) && (qual_data)),
	.wb_adr_i(proc_addr[2:0]),
	.wb_dat_i(proc_data[7:0]),
	.wb_dat_o(i2c1_data_out[7:0]),
	.wb_we_i(~proc_rw),
	.wb_stb_i((qual_counter[1:0] == 2'h2) && (proc_addr[15:4] == I2C_REG_ADDR1)),
	.wb_cyc_i((qual_counter[1:0] == 2'h2) && (proc_addr[15:4] == I2C_REG_ADDR1)),
	.wb_ack_o(ack_1),
	.wb_inta_o(i2c1_irq_o),
	.scl_pad_i(scl1_pad_i),
	.scl_pad_o(scl1_pad_o),
	.scl_padoen_o(scl1_padoen_o),
	.sda_pad_i(sda1_pad_i),
	.sda_pad_o(sda1_pad_o),
	.sda_padoen_o(sda1_padoen_o)
	);

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