A Color Vision System for Embedded Robotics Applications

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Verilog FPGA standard fifo, used everywhere:

module fifo_33 #(parameter fifo_width = 33) (
			input wire clk,
			input wire rst,
			input wire [fifo_width - 1:0] din,
			input wire we,
			output wire [fifo_width - 1:0] dout,
			input wire re,
			output wire full,
			output wire empty
			);

////////////////////////////////////////////////////////////////////
//
// Local Wires
//

reg     [fifo_width - 1:0]	mem[0:3];
reg     [1:0]   wp;
reg     [1:0]   rp;
wire    [1:0]   wp_p1;
wire    [1:0]   rp_p1;
reg		gb;

////////////////////////////////////////////////////////////////////
//
// Misc Logic
//

always @(posedge clk or posedge rst)
begin
	if(rst)
		wp <= #1 2'h0;
   else if(we)
		wp <= #1 wp_p1;
end

assign #1 wp_p1 = wp + 2'h1;

always @(posedge clk or posedge rst)
begin
	if(rst)
		rp <= #1 2'h0;
	else if(re)
		rp <= #1 rp_p1;
end

assign #1 rp_p1 = rp + 2'h1;

// Fifo Output
assign dout = mem[rp];

// Fifo Input 
always @(posedge clk)
begin
	if(we)
		mem[wp] <= #1 din;
end

// Status
assign #1 empty = (wp == rp) & !gb;
assign #1 full  = (wp == rp) &  gb;

// Guard Bit ...
always @(posedge clk)
begin
	if(rst)
		gb <= #1 1'b0;
	else if((wp_p1 == rp) & we)
		gb <= #1 1'b1;
	else if(re)
		gb <= #1 1'b0;
end

endmodule

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