A Color Vision System for Embedded Robotics Applications

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Verilog FPGA color blob detection code:

//=========================================================
//
//  DJ's verilog code for blob detection
//
//  Written By: Kenneth Y. Maxon - 03/17/2004
//
//=========================================================

module blob_detection(
			input wire sys_clock,
			input wire force_reset,

			input wire [7:0] line_count,
			input wire [8:0] pixel_count,
			input video1_out_strb,
			
			input wire video_filter_data_valid,
			input wire end_of_screen_capture,
			input wire beginning_of_screen_capture,
			
			output wire [23:0] x_output,
			output wire [23:0] y_output,
			
			output wire blob_capture_done
			);

wire divide1_done_flag;
reg [23:0] running_x_counter;
reg [23:0] running_y_counter;
reg [16:0] running_num_counter;

always @(posedge sys_clock)
	if(beginning_of_screen_capture)
	begin
		running_x_counter[23:0] <= #1 24'h000000;
		running_y_counter[23:0] <= #1 24'h000000;
		running_num_counter[16:0] <= #1 17'h00000;
	end
	else if(video_filter_data_valid && video1_out_strb)
	begin
		running_x_counter[23:0] <= #1 running_x_counter[23:0] + pixel_count[8:0];
		running_y_counter[23:0] <= #1 running_y_counter[23:0] + line_count[7:0];
		running_num_counter[16:0] <= #1 running_num_counter[16:0] + 17'h00001;
	end

//=======------------*** serial divider #1

serial_divide_uu #(24,24,0,0,5,1) my1_divider(
			.clk_i(sys_clock),
			.clk_en_i(1'b1),
			.rst_i(force_reset),
			.divide_i(end_of_screen_capture),
			.dividend_i(running_x_counter[23:0]),
			.divisor_i({7'h0,running_num_counter[16:0]}),
			.quotient_o(x_output[23:0]),
			.done_o(divide1_done_flag)
			);


serial_divide_uu #(24,24,0,0,5,1) my2_divider(
			.clk_i(sys_clock),
			.clk_en_i(1'b1),
			.rst_i(force_reset),
			.divide_i(end_of_screen_capture),
			.dividend_i(running_y_counter[23:0]),
			.divisor_i({7'h0,running_num_counter[16:0]}),
			.quotient_o(y_output[23:0]),
			.done_o()
			);


assign #1 blob_capture_done = divide1_done_flag;

endmodule

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